A VLSI fuzzy logic inference engine for real-time process control
W.D. Dettloff, K.E. Yount · 1989
The single-chip implementation of a general-purpose fuzzy logic inference engine is described. Features include a dynamically reconfigurable and cascadable architecture, TTL (transistor-transistor logic)-compatible host interface, laser-programmed redundancy, special mode for testability, RAM rule storage, and on-chip fuzzification and defuzzification. Up to 102 parallel rules can be processed in real-time control applications by utilizing a 1-μm, 3.3-V DLM CMOS technology. 580 KFLIPS (fuzzy logic inferences per second) are attained using 688 K transistors and 36-MHz operation