Embedded deterministic test for low-cost manufacturing
Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer, Jun Qian · IEEE Design & Test of Computers · 2003
You have probably heard that BIST takes too long and its fault coverage is low, and that deterministic test requires too many patterns. This article shows how on-chip compression and decompression techniques provide high fault coverage with low test times.