Power‐gating technique for network‐on‐chip buffers
Mario R. Casu, Monika Yadav, Maurizio Zamboni · Electronics Letters · 2013
A new approach to reducing leakage power in network‐on‐chip buffers is presented. The non‐uniformity of buffer utilisation is leveraged across the network and power‐gating is applied to scarcely utilised buffers. Instead of turning‐off the buffers completely, a buffer portion is kept turned‐on. This design choice has a significant performance benefit because the buffer is always able to receive network packets. Design aspects and trade‐offs in a 45 nm CMOS technology are discussed and results obtained over video application benchmarks are presented. It is shown that it is possible to reduce buffer leakage by 40% without performance penalty.