Novel Flexible Systolic Mesh Architecture for Parallel VLSI Implementation of Finite Digital Convolution
Basant Kumar Mohanty, Pramod Kumar Meher · IETE Journal of Research · 1998
The paper presents a fully systolic mesh architecture for high-speed implementation of finite digital convolution. The proposed structure is fully pipelined, and maintains regular, as well as local interconnections. It has achieved significant reduction in latency and increase in throughput rate over the existing structure with less than proportionate increase in the hardware. Apart from these, it requires a small cycle period and offers considerable saving of latches.