A Test Concept for a DSP based Codec
Peter Caldera · European Solid-State Circuits Conference · 1994
The increasing performance of chips nowadays demands new test strategies allowing short test time together with a high fault coverage. To decrease the overall test costs board as well as system tests must be supported. Therefore the test concept has to be developed in a very early step of system and circuit design in cooperation with the customer. In this paper a test concept for a DSP based codec including digital and analog BIST will be presented