A hidden surface and shading processor (HSSP) with a systolic architecture
Teiji Nishizawa, T. Ohgi, Hiroyuki Kamiyama, Kenji NAGATOMI, K. Maenobu · IEEE Journal of Solid-State Circuits · 1988
The HSSP processor for 3-D graphics applications is described. The HSSP chip has a regular structure owing to a skewed systolic array architecture. This novel VLSI-oriented architecture was applied to real-time 3-D graphics image generation, which requires very high processing throughput. The HSSP eliminates hidden portions of surfaces from a viewer, and gives a constant intensity or a smooth shaded intensity to each surface. It uses a scan-line Z-buffer algorithm, and outputs the resulting image in the scan line, pixel by pixel in a serial manner. The chip is fabricated in 1.2- mu m twin-tub CMOS technology. It contains 330 K transistors on a 11.06*11.05-mm die, and operates with a 20-MHz single-phase clock.>