Linear phase FIR digital filters using interpolated equalizers
Hitoshi Honma, Masakazu Yamada, Masahiko Sagawa · Electronics and Communications in Japan (Part III Fundamental Electronic Science) · 1989
Abstract A method for designing an FIR digital filter is reported with a view to reducing the number of multipliers and addres. an effective method for reducing the number of multipliers and addres is the one in which a prefilter without a multiplier and an equalizer (compensating the characteristics to satisfy the given specifications) are cascaded. In previous studies on this method, the design of the prefilter was the main topic and no sufficient attention was given to the equalizer. In the present method, the design method of the equalizer is also studied. A new design method for an equalizer is proposed in which a concept of interpolation is introduced. the present method is applied to a number of examples. It is confirmed that a significant reudtion of the number of multipliers and addres is obtained.