FPGA implementation of image component labeling
Danny Crookes, Khaled Benkrid · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1999
Connected Component Labelling is an important task in intermediate image processing. Several algorithms have been developed to handle this problem. Hardware implementations have typically been based on massively parallel architectures, with one logical processing element per pixel. This approach requires a great deal of logic, so current solutions are often implemented in VLSI rather than on FPGAs, and are limited in the size of image which can be labelled.