Performance and energy limits of a processor-integrated FFT accelerator
Tung Thanh-Hoang, Amirali Shambayati, Calvin Deutschbein, Henry Hoffmann, Andrew A. Chien · 2014
Accelerators have long been used to improve the performance and energy efficiency of embedded signal processing systems relying on Fast Fourier Transforms (FFTs). We explore the benefits of processor-integrated FFT accelerators, characterizing their performance and energy efficiency for current and future memory architectures. First, we consider designs that deeply integrate an FFT accelerator into a simple 5-stage RISC pipeline and evaluate the performance and energy efficiency for a 32 nm process. Our results indicate that a 64-point processor-integrated FFT accelerator alone can increase performance for a 4K/32k-point 1D-FFT by 7/4-fold respectively. In term of energy efficiency, our 64-point FFT accelerator increases it at least 4-fold. Second, since memory performance is a critical constraint, we evaluate system configuration with 3D-stacked DRAM systems. Our results indicate that energy efficiency bottlenecks can be alleviated, as the 3D-stacked memory reduces energy by nearly 14-fold. When combined with our FFT accelerator, overall energy efficiency for 4k and 32k-point FFTs increases 86-fold and 70-fold respectively. Prospectively, with addition of a data layout transformation engine, cycle count and energy for the data transpose phase can be reduced 10x. Such a step would increase the accelerator benefit at least 10-fold in energy for DDR3 and more than 100-fold in 3D-stacked memory system.