Evaluation of Performance Optimal Tree Based Application Specific Network on Chip Architectures
Kishore K. Yalamanchili, Aditya Pasalapudi, Apurva Dargar, Saransh Mehrotra, Harshal Ved · 2009
In the paradigm of Network on chip, design decisions at various levels of hierarchy are to be made based on timing, power and area constraints. Topology design is one of the most important parts of a NoC design, with design decision affected by constraints in all the three parameters. Tree based structures are one of the most commonly used and basic network on chip architectures, in addition to generic structures like 2-D Mesh. In this paper, we present the area and power comparisons for some of the tree based NoC architectures optimized for performance, with Video Object Plane Decoder (VOPD) as the case study. We also present a comparison with 2-D Mesh architecture and educe the trend followed in the area and power parameters.