Implementation of high-speed SHA-1 architecture
Eun-Hee Lee, Je-Hoon Lee, Il-Hwan Park, Kyoung-Rok Cho · IEICE Electronics Express · 2009
This paper proposes a new SHA-1 architecture to exploit higher parallelism and to shorten the critical path for Hash operations. It enhances a performance without significant area penalty. We implemented the proposed SHA-1 architecture on FPGA that showed the maximum clock frequency of 118MHz allows a data throughput rate of 5.9Gbps. The throughput is about 26% higher, compared to other counterparts. It supports cryptography of high-speed multimedia data.