A priority assignment strategy of processing elements over an on-chip bus
Ya-Shu Chen, Song-Jian Tang, Shi-Wu Lo · 2007
The number of bus transactions in System-on-Chip (SoC) grows significantly in recent years. Because of different timing constraints for different applications, how to find a proper priority assignment for processing elements (PEs) of SoC becomes very challenging. In this paper, we first show that the priority assignment problem with one unique priority for each PE is NP-complete. When each bus transaction can have one unique priority, we propose an optimal priority assignment algorithm for a given workload. We then propose a priority assignment strategy based on Simulated Annealing (SA) for PEs, where bus arbitration is done in a priority-driven fashion. The objective is to minimize the number of priorities needed for each PE and to satisfy the timing constraints of applications. The experimental results show some encouraging results in priority assignment.