An RTL Methodology to Enable Low Overhead Combinational Testing
Subhrajit Bhattacharya, Sujit Kumar Dey, Bhaskar Sengupta · 1997
This paper introduces RT-SCAN, a register transfer (RT) level test synthesis technique which enables the testing of complex sequential circuits by combinational test patterns without the use of scan, eliminating the high overheads associated with full-scan testing. The methodology involves both DFT to prepare the sequential circuit for combinational testing, as well as synthesizing the necessary sequential circuit input patterns from the given combinational test patterns. Unlike the existing high-level methods, the new approach is applicable to any general design, including control-flow intensive designs, where the control-flow and hence random logic, multiplexors, counters (incrementers), buses, and registers, dominate the circuit, with the existence of a few arithmetic units.