An HMAC processor with integrated SHA-1 and MD5 algorithms
Mao-Yin Wang, Chih-Pin Su, Chih-Tsun Huang, Cheng‐Wen Wu · 2004
Abstract—Cryptographic algorithms are prevalent and important in digital communications and storage, e.g., both SHA-1 and MD5 algorithms are widely used hash functions in IPSec and SSL for checking the data integrity. In this paper, we propose a hardware architecture for the stan-dard HMAC function that supports both. Our HMAC de-sign automatically generates the padding words and reuses the key for consecutive HMAC jobs that use the same key. We have also implemented the HMAC design in silicon. Compared with existing designs, our HMAC processor has lower hardware cost—12.5 % by sharing of the SHA-1 and MD5 circuitry and a little performance penalty. I.