Design of a 256-KBit EEPROM IP for touch-screen controllers
Gyu-Sam Cho, Du-Hwi Kim, Jihye Jang, Moo-Hun Park, Pan-Bong Ha, Young‐Hee Kim, Jung‐Hwan Lee · 2010
We propose a compact design having low-power and high-speed EEPROM for touch-screen controller ICs. To optimize a small-area EEPROM design, a SSTC (side-wall selective transistor) cell is proposed which involves repeated high-voltage switching circuits inside the EEPROM core circuit. A digital data-bus sensing amplifier circuit is proposed as a low-power technology. For high speed, the distributed data-bus scheme is applied, and the driving voltage for both the EEPROM cell and the high-voltage switching circuits uses VDDP (=3.3V) which is higher than the logic voltage, VDD (=1.8V), using a dual power supply. 256-KBit EEPROM IP is designed using MagnaChip's 0.18μm EEPROM process. The layout size of the designed 256-KBit EEPROM IP is 1765.05 μm × 691.71 μm.