Finite field polynomial 16-bit multiplier for power constrained devices
Jose Antonio Flores Escobar, Moisés Salinas-Rosales, José Velázquez López · 2012
In this work a finite field polynomial multiplier is presented. The multiplier is based on two-step algorithm performing the multiplication with the add and shift algorithm. A FPGA was chosen to implement the multiplier design, resulting the multiplication performed on 256 AND gates.