Low power asynchronous DSP for digital mobile phones
M. Lewis · 2001
The C A D S digital signal processor @SP) architecture is presented.This DSP is intended for use in digital mobile phones and, in this application, it is necessary to balauce the requirement of high processing throughput with the demand of low power for extended battery lifetime.These requirements are addressed by a multi-level power reduction strategy, involving the use of a parallel asynchronous archikcture, a configurable compressed instruction set, a large register iile, the use of signmagnitude arithmetic, and reduced support for intemrpts.