An active buffer sizing algorithm for power-efficient NoC
Junhui Wang, Yue Qian, Jia Lü, Baoliang Li, Wenhua Dou · 2014
In network-on-chips (NoCs), how to reduce the power consumption of router buffers has been a major concern. In this paper, we propose a methodology to minimize the power consumption of routers with meeting all the deadlines of traffic flows. First, we present a network calculus-based method to analyze the worst-case delay of each flow in NoC. By using the method, an active buffer sizing algorithm is proposed. The algorithm can find the optimal active size of each buffer, by iteratively reducing the size of active buffer units and checking if the deadlines are still met. Finally, the experimental results show that our method can save at most 20% of the total power consumption for NoC.