A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture
H. Noda, Kazunari Inoue, M. Kuroiwa, F. Igaue, Koji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, A. Amo, A. Hachisuka, S. Soeda, Isamu Hayashi, Fukashi Morishita, Katsumi DOSAKA, Kazutami Arimoto, Kazuyasu Fujishima, Keiko Anami, Tatsuhiko Yoshihara · IEEE Journal of Solid-State Circuits · 2005
This paper describes a 4.5-Mb dynamic ternary CAM (DTCAM) which is suitable for networking applications. A dynamic TCAM cell structure in 130-nm embedded DRAM technology is used to realize the small cell size of 3.59 /spl mu/m/sup 2/. In addition, a novel array architecture of TCAM, the pipelined hierarchical searching (PHS) architecture, is proposed. The PHS architecture is found to be suitable for realizing small area penalty, high-throughput searching and low-voltage operation simultaneously. With the combination of the DTCAM cell and the PHS architecture, small silicon area of 32 mm/sup 2/ for a fabricated 4.5-Mb DTCAM chip, high performance of 143 M searches per second and low power dissipation of 1.1 W have been achieved. To improve the yield of TCAMs, a novel shift redundancy technique is applied and estimated to result in 3.6-times yield improvement. These techniques and architectures described in this report are attractive for realizing cost-efficient, large-scale, high-performance TCAM chips.