Synthesize of High Speed Floating-point Multipliers Based on Vedic Mathematics
S. Anjana, C. Pradeep, Philip Samuel · Procedia Computer Science · 2015
This work proposes designing of high speed floating point multipliers. The multipliers are designed using Vedic Mathematics. The Vedic Multiplier (VM) has a regular structure therefore can be easily layout in a Silicon chip. Two different VMs are designed with different adder structures viz. Ripple Carry Adder (RCA) and Carry Look-ahead Adder (CLA). A single precision floating point multiplier is designed with these two VM structures. The multipliers are structurally modeled in Verilog HDL. The simulation and synthesis are done in Xilinx® ISE 14.2. A comparison on the basis of area, power and delay is performed on Virtex-5 (xc5vlx110tff1136-1).