A real-time, low latency, FPGA implementation of the 2-D discrete wavelet transformation for streaming image applications
O. Benderli, Y.Ç. Tekmen, N. Ismailoglu · 2003
In this paper, we present an architecture and a hardware implementation of the 2D Discrete Wavelet Transformation (DWT) for applications where row-based raw image data is streamed in at high bandwidths and local buffering of the entire image is not feasible. The architecture is especially suited for multi-spectral imager systems, such as on board an imaging satellite, however can be used in any application where time to next image constraints require real-time processing of multiple images. The latency that is introduced as the images stream through the DWT filter and the amount of locally stored image data is a function of the image and tile size. For an n/sub 1/ /spl times/ n/sub 2/ size image processed using (n/sub 1//k/sub 1/) /spl times/ (n/sub 2//k/sub 2/) sized tiles the latency is equal to the time elapsed to accumulate a (1/k/sub 1/) portion of one image. In addition, a (2/k/sub 1/) portion of each image is buffered locally. The proposed hardware has been implemented on an FPGA and is part of a JPEG2000 compression system designed as a payload for a Low Earth Orbit (LEO) micro-satellite, which will be launched in August 2003.