Test pattern generation for CMOS ternary logic
C. Rozon, H.T. Mouftah · International Journal of Electronics · 1988
Multiple-valued logic has been proposed to overcome some of the problems associated with the complexity of VLSI circuits. Circuit design and hardware implementation of multiple-valued devices in various standard binary VLSI processes have been the subject of much research over the recent years and many useful applications have emerged. It is also important to study the testability of these circuits to promote their acceptance by the electronics industry. This paper presents a new Path Oriented Algorithm for Ternary Logic (POAFTEL) which can be used to generate test patterns for combinational CMOS ternary logic. These patterns can also be used in testing CMOS ternary scan-based designs.