Live demonstration: FPGA based 3840×2160 video decoding and displaying system
Haoming Zhang, Dajiang Zhou, Satoshi Goto · 2014
A demonstration of FPGA-based 3840×2160 UHDTV (Ultra-high definition TV) H.264 video decoding and displaying system is proposed in this paper. The proposed system can decode and display 3840×2160 video by two Altera Stratix III DE3 FPGA boards, which are connected together with each other by HSTC cable. Video processing system requires high memory bandwidth. This paper locate decoder module and display module in different FPGA board and try to use two off-chip memory of the two boards, in order to provide more memory bandwidth.