Low Complexity Bit-Parallel Squarer for GF(2n) Defined by Irreducible Trinomials
S.-M. PARK · IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences · 2006
We present a bit-parallel squarer for GF(2n) defined by an irreducible trinomial xn + xk + 1 using a shifted polynomial basis. The proposed squarer requires TX delay and at most ⌈n/2⌉ XOR gates, where TX is the delay of one XOR gate. As a result, the squarer using the shifted polynomial basis is more efficient than one using the polynomial basis except for k = 1 or n/2.