Formal verification method for combinatorial circuits at high level design
Junji Kitamichi, H. Kageyama, Nobuo Funabiki · 1999
In this paper, we propose a formal verification method for combinatorial circuits at high level design. The specification is described by both integer and Boolean variables for input and output variables, and the implementation is described by only Boolean variables. Our verification method judges the equivalence between the specification and the implementation by deciding the truth of the Presburger sentence. We show experimental results on some benchmarks, such as a 4 bit ALU and multiplier, by our method.