Clock skew minimization during FPGA placement
Kai Zhu, Martin D. F. Wong · 1994
Unlike traditional ASIC technologies, the geometrical structures of clock trees in an FPGA are usually xed and cannot be changed for dierent circuit designs.Moreover, the clock pins are connected to the clock trees via programmable switches.As a result, the load capacitances of a clock tree may b e c hanged, depending on the utilization and distribution of logic modules in an FPGA.It is possible to minimize clock s k ew by distributing the load capacitances, or equivalently the logic modules used by the circuit design, carefully according to the circuit design.In this paper we present an algorithm for selecting logic modules used for circuit placement such that the clock s k ew is minimized.The algorithm can be applied to a variety of clock tree architectures, including those used in major commercial FPGAs.Furthermore, the algorithm can be extended to handle buered clock trees and multi-phase clock trees.Experimental results show that the algorithm can reduce clock s k ews signi cantly as compared with the traditional placement algorithms which do not consider clock s k ew minimization.