A content addressable memory management unit with on-chip data cache
A. K. Goksel, R.H. Krambeck, P. Thomas, M.-S. Tsay, C. Y. Chen, D.G. Clemons, F. D. LaRocca, L.-P. Mai · IEEE Journal of Solid-State Circuits · 1989
The design of a single chip (WE-32201) that includes both a content-addressable memory-based management unit and a large data/instruction cache is described. The chip belongs to AT&T's WE-32200 chip set and is fabricated using a 1 mu m twin tub CMOS process. It boosts the performance of the entire chip set significantly by providing high memory bandwidth and virtual-memory-management support. The combination of high-performance circuit design and system architectural design techniques makes the chip a major enhancement to the chip set.>