VLSI Implementation Of The Fast Fourier Transform
Paul M. Chau, Walter H. Ku · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1986
A VLSI implementation of a Fast Fourier Transform (FFT) processor consisting of a mesh interconnection of complex floating-point butterfly units is presented. The Cooley-Tukey radix-2 Decimation-In-Frequency (DIF) formulation of the FFT was chosen since it offered the best overall compromise between the need for fast and efficient algorithmic computation and the need for a structure amenable to VLSI layout. Thus the VLSI implementation is modular, regular, expandable to various problem sizes and has a simple systolic flow of data and control. To evaluate the FFT architecture, VLSI area-time complexity concepts are used, but are now adapted to a complex floating-point number system rather than the usual integer ring representation. We show by our construction that the Thompson area-time optimum bound for the VLSI computation of an N-point FFT, area-time2oc = ORNlogN)1+a] can be attained by an alternative number representation, and hence the theoretical bound is a tight bound regardless of number system representation.