Design rewiring based on diagnosis techniques
Andreas G. Veneris, Magdy S. Abadir, Ivor Ting · 2001
Logic optimization is the step of the VLSI design cycle where the designer performs modifications on a design to satisfy di#erent constraints such as area, power or delay. Recently, ATPG-based design rewiring techniques for logic optimization have gained increasing popularity. In this paper we propose a novel ATPG-based design rewiring methodology that borrows from previous design error diagnosis and correction techniques. We also present examples and experiments that indicate the added potential of our approach which is expected to provide a "powerful" route to design optimization. 1 Introduction Logic optimization is the step of the VLSI design cycle where the designer modifies the netlist obtained by synthesis tools to achieve di#erent constraints such as minimize the area, reduce power consumption, satisfy timing constraints, reduce switching noise or improve the testability of the final circuit. Recently, ATPG-based optimization techniques [6] [7] [8] [9] [10] [12] have gained i...