High-level test synthesis based on controller redefinition
Víctor Fernández, Pablo Sánchez · Electronics Letters · 1997
A novel approach is proposed for the high-level synthesis of data-dominated circuits. The functionality of the controller is redefined in order to improve the testability of the final circuit. The data path is left untouched. Test results are obtained at gate-level, after the RT synthesis process, with a sequential test generation package, HITEC.