Processing while routing: a network-on-chip-based parallel system
Silvio Roberto Fernandes, Rodrigo Cardoso de Oliveira, M. Costa, Ivan Saraiva Silva · IET Computers & Digital Techniques · 2009
Technology integration has increased to the point where the development of multi-core processor architectures is a market reality nowadays. In this scenario, the interconnection network has a critical function when the number of cores increases, since it is impossible to use bus-based solutions. Other interconnection solutions have been employed. However, they are area and power expensive. This paper approaches this problem with a new NoC-based architecture and a new computation mode. It proposes the utilisation of network-on-chip not only as interconnection but also as the processing datapath.