New Bit-Parallel Systolic Multiplier over GF(2m) Using The Modified Booth's Algorithm
Chiou‐Yng Lee, Yu-Hsin Chiu, Che Wun Chiou · 2006
A new algorithm for the multiplication of two elements in GF(2m) based on the modified Booth's algorithm is presented. The proposed algorithm permits efficient realization of the multiplexer-based bit-parallel multiplication using iterative arrays. The latency of the multiplier has 3m/2 clock cycles. For the estimated complexity of the proposed multiplier, we take into the transistor count using a standard CMOS VLSI realization. Our analysis shows that, in terms of the time and the space complexities, the multiplexer-based array architecture is the better choice for our proposed bit-parallel systolic multiplier