Exploiting DMA for Performance and Energy Optimized STREAM on a DSP
Gilbert Netzer, Lennart Johnsson, Daniel Ahlin, Eric J. Stotzer, Pekka Varis, Erwin Laure · 2014
Energy efficiency is of major concern in HPC. DSP architectures have the potential to offer highly competitive energy efficiency for applications requiring 64-bit floating-point precision. For STREAM, we achieved 1.47GB/J energy efficiency and 96% DDR3 memory bandwidth utilization on the Texas Instruments TMS320C6678 DSP by using its DMA engines for prefetching to avoid cache misses, which cause pipeline stalls in the DSP's cores, and to prevent write-allocate loads, which would significantly reduce performance. The DMA engines were also used to coordinate the DSPs cores and schedule main memory accesses to improve DDR3 bandwidth utilization. We briefly describe the instrumentation that we designed and implemented for accurate measurement of the core-related, on-chip memory, and DDR3 power consumption and the effectiveness of the DSP's power saving mechanisms to trade-off performance and energy efficiency.