Low power system scheduling and synthesis
Niraj Kumar Jha · International Conference on Computer Aided Design · 2001
Many scheduling techniques have been presented recently which exploit dynamic voltage scaling (DVS) and dynamic power management (DPM) for both uniprocessors, and distributed systems, as well as both real-time and non-real-time systems. While such techniques are power-aware and aim at extending battery lifetimes for portable systems, they need to be augmented to make them battery-aware as well. This paper surveys such power-aware and battery-aware scheduling algorithms. In addition system synthesis algorithms for real-time systems-on-a-chip (SOCs), distributed and wireless client-server embedded systems, etc., have begun optimizing power consumption in addition to system price. The paper also surveys such algorithms as well, and points out some open problems.