Computational complexity of test generation for ETG PLAs
Yinghua Min, Yashwant K. Malaiya, Bidyut Gupta · IEE Proceedings E Computers and Digital Techniques · 1989
In a wide sense, easy test generation (ETG) circuits can be considered as design for testability (DFT) circuits. However most of the DFT techniques presented so far in the literature are attempts to ease test application. Major disadvantages with these DFT techniques are degradation of circuit performance, and often the requirement of a long and continuous test mode. However, an ETG circuit attempts to make test generation easier without any significant degradation of circuit performance, and the test mode can be divided into pieces to fit the requirement of real-time systems. The paper presents two important types of PLA design techniques which reduce the computational complexity for test generation. An O(n) ETG PLA is defined, and a sufficient condition for O(n2) ETG PLAs is also obtained. It is shown that the easily testable PLAs introduced by Bozorgui-Nesbat and McCluskey are O(n2) ETG PLAs.