A performance study of a highly-parallel architecture to provide registration and translation services in an intelligent network
Jerry Stach, Jerry Place · 1992
This paper presents the initial investigation of a highly parallel architecture that can be used as an Intelligent Network Translation and Registration Platform (INTARP). The INTARP architecture is deterministic and uses a hyper-switch as well as bus connections to pass messages. Threads through the multiprocessing pipelines are maintained by service definitions of the call procedures on “anchor processors”. The processes call procedures distributed over “sequencing processors”. INTARP is being prototyped using the inMOS, family of transputers. Unlike other architectures designed for the Intelligent Network, INTARP is designed specifically to minimize the post dial delay (PDD) the architecture contributes to circuit switch call processing. Unmanaged PDD in the Intelligent Network can lead to higher call abandonments. PDD also increase trunk and port capitalization due to the greater call holding time in peripheral processors prior to information transfer. The INTARP architecture is evaluated using a simulation model. Translation, PCN Registration and Calling Card services have been implemented on the simulation model and the performance of the architecture is inferred from the performance of the simulation studies.