Fast pipelined pseudo-random number generator in programmable SoC device
P. Dąbal, Ryszard Pelka · 2014
In this paper we propose a novel architecture of chaotic pseudo-random number generator (PRNG) based on the pipelined processing and frequency dependent negative resistances (FDNR). The design of PRNG has been optimized to achieve maximum output rate of pseudo-random sequences. The PRNG has been tested for 16-, 32-, 48-, and 64-bit precision of arithmetic by NIST 800-22 tests performed for each individual bit position. Then, the selected bit positions have been composed into the final output stream and verified by NIST test again. The PRNG has been implemented in programmable SoC device from Xilinx. Using the Zynq-7000 chip with 28-nm programmable logic and dual core ARM Cortex-A9 we get the maximum generation rate equal to 11.48 Gbps. An efficiency of the proposed approach in terms of maximum throughput and required logic resources has been compared with other implementations of chaotic PRNGs in programmable devices.