Directions in future of SRAM with QDR-WideIO for high performance networking applications and beyond
Ali Reza Keshavarzi, Dinesh Maheshwari, Derwin Mattos, Ravi Kapre, Sandeep Krishnegowda, Morgan Whately, Sudhir Gopalswamy · 2014
In this paper we describe the high performance synchronous QDR-WideIO SRAM KGD from Cypress that is architected with fast and wide interface with optimized memory sub-system for future high performance networking and computing applications. Systems for next generation networking switches rely on high rate router line cards of 200 to 400 Gbps. QDR-WideIO fabricated on 28nm HKMG technology builds upon High Bandwidth Memory (HBM) interface standard while using 2.5D/3D stacking to form a System in Package (SiP) networking system solutions. We explain that both SRAM and DRAM are necessary and can co-exist in these systems and why it does not make sense to integrate the SRAM inside the logic ASIC. We also describe the memory design and partitioning that allows for delivering requisite Random Transaction Rate (RTR) representing random accesses to the memory per second of approaching 24000 MT/s (>10X improvement over our previous generation of QDR-IV synchronous SRAM) and total bandwidth of greater than 1.5 Tbps in a power efficient way. QDR-WideIO achieves latency of 13 cycles for read and 8 cycles for write with density of 288Mb with core operating at 1500 MHz. Finally we describe a path forward toward future of in-package integrated products.