On Delay Fault Testing in Logic Circuits
Chin Jen Lin, Sudhakar M. Reddy · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1987
Correct operation of a logic circuit requires propagation delays of all paths in the circuit to be smaller than the intended "clock interval." Random or deterministic tests, conducted at the normal clocking rate, can be used to insure that path delays in manufactured circuits meet the specifications. Algorithms, based on a five-valued logic system, to accurately calculate the detection probability of path delay faults by random delay tests as well as to derive deterministic tests to detect path delay faults are proposed. The results can be used to determine the test length for a desired confidence level in testing a path fault when random tests are used, and to generate a test set for a list of delay faults when deterministic tests are used.