Optimal implementation approach for discrete wavelet transform using FIR filter banks on FPGAs
Joe J. Sargunaraj, Sathyanarayan S. Rao · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1998
We present a wavelet transform implementation approach using a FIR filter bank that uses a Wallace Tree structure for fast multiplication. VHDL models targeted specifically for synthesize have been written for clocked data registers, adders and the multiplier. Symmetric wavelets like Biorthogonal wavelets can be implemented using this design. By changing the input filter coefficients different wavelet decompositions may be implemented. The design is mapped onto the ORCA series FPGA after synthesis and optimization for timing and area.