Code generator optimizations for the ST120 DSP-MCU core
Benoît Dupont de Dinechin, F. de Ferri, Christophe Guillon, Arthur Stoutchinin · 2000
The ST120 Digital Signal Processor -Micro-Controller Unit (DSP{MCU) core was designed by STMicroelectronics in order to meet the ever-increasing digital signal processing requirements of portable and consumer applications.Like other recent high-end DSP{MCU cores, the ST120 blends traditional DSP features with modern Instruction-Level Parallelism (ILP) capabilities.Compiler management o f the ST120 features presents a unique challenge to the code generation.The ST120 Linear Assembly Optimizer (LAO) eectively exploits instructionlevel parallelism, while enabling compact code size.In this paper, we focus on the LAO implementation of the SSA representation, the IF-conversion, the SLIW scheduling, and the LAO i m p r o vements to register allocation.This includes solutions to problems that arise when compiler optimizations are applied to assembly-level, already predicated code.Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific