A Code Partitioning Tool for Simulink Models to Implement on FPGA-Based Network-on-Chip Architecture
Satoru Miyasono, Yosuke Moriai, Hiroshi Saito · 2014
In this paper, we propose a code partitioning tool to implement application C codes generated from a Simulink model into FPGA-based network-on-chip (NoC) architecture. First, we propose our FPGA-based NoC architecture with communication functions for sending and receiving data on the NoC. Our code partitioning tool accepts application C codes generated from a Simulink model, communication functions, and the task scheduling and allocation result for the Simulink model as inputs. Then, our proposed code partitioning tool generates C codes for each processing core on the NoC by copying the application C codes, generating a behavior function, inserting the communication functions, and removing unnecessary code based on the task scheduling and allocation result. In the experiments, we evaluate the execution time and the code size when we implement three Simulink models on our NoCs using our code partitioning tool.