Functional vector generation for HDL models using linear programming and 3-satisfiability
Farzan Fallah, Srinivas Devadas, Kurt Keutzer · 1998
Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model describes interconnections of arithmetic, logic and memory modules. Given a path in the HDL model, the search for input stimuli that exercise the path can be converted into a standard satisfiability checking problem by expanding the arithmetic modules into logic-gates. However, this approach is not very efficient.