Design of a low power Digital Down Converter for 802.16m - 4G WiMAX on FPGA
Sudhir Rao Rupanagudi, Varsha G. Bhat, S. Hemalatha, N. Bhavana, MHETRE ARCHANA, B.V. Chandrika, Ramachandran Ashwini, Keerti G. Torvi, S Darshan, B.G. Abhilash, Kumar Singh Anil, Vinayak Swamy K.M. · 2014
The Digital Down Converter also known as the DDC is one of the most integral parts of a baseband wireless receiver system. The major function of the DDC is to down convert an Intermediate Frequency (IF) signal to Baseband. It achieves this by performing complex tasks such as mixing, decimation and filtering and it is due to this reason, the architecture of the DDC occupies a significant on-chip area and consumes a large amount of power as well. In this paper, a novel methodology to implement the DDC architecture has been presented. The paper focuses on the 4G WiMAX standard. The DDC has been designed and implemented on a Xilinx Virtex 4 FPGA utilizing a CORDIC based NCO, Vedic math based mixer and a CIC based filter. A 93% reduction in area was achieved and a 3.5 times reduction in power with respect to previous architectures has also been attained.