An Alternating Spacer AES Crypto-processor
Julian P. Murphy, Alex Yakovlev · Proceedings of ESSCIRC · 2006
An AES crypto-processor has been fabricated to investigate the security properties of an alternating spacer dual-rail logic style and a security based design flow; which introduces a previously unused state in differential power-balancing. The fruits of which offer a tangible solution to information leakage during the life-time of a smartcard's secret key, whilst crucially keeping the usually expensive costs of increased smartcard security to a minimum: design economics, area and power. Power analysis on the device results in a forty fold increase in the number of power measurements needed to crack the 128-bit secret key over an unmodified and architecturally identical design. Area is only increased by 88% compared to 3-4times in other reported power-balancing methods (Pop, 2005)