VLSI Architectures For Block Matching Algorithms
P. Pirsch, T. Komarek · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1988
This paper discusses architectures for realization of block matching algorithms with emphasis on highly concurrent systolic array processors. A three step mapping methodology for systolic arrays known from the literature is applied to block matching algorithms. Examples of 2-dimensional and 1-dimensional systolic arrays are presented. The needed array size, the transistor count and the maximum frame rate for processing video telephone and TV signals have been estimated.