Efficient Test Data Compression and Decompression for System-on-a-Chip using Internal Scan Chains and Golomb Coding
Anshuman Chandra, Krishnendu Chakrabarty · 2001
We present a data compression method and decompression architecture for testing embedded cores in a system-ona -chip (SOC). The proposed approach makes effective use of Golomb coding and the internal scan chains of the core under test, and provides significantly better results than a recent compression method that uses Golomb coding and a separate cyclical scan register (CSR). The use of the internal scan chain for decompression obviates the need for a CSR. In addition, the novel interleaving decompression architecture allows multiple cores in an SOC to be tested concurrently using a single ATE I/O channel. We demonstrate the effectiveness of the proposed approach by applying it to the ISCAS 89 benchmark circuits. 1 Introduction System-on-a-chip (SOC) designs consisting of intellectual property (IP) cores present a number of difficult test challenges [1]. The volume of test data for an SOC is growing rapidly as IP cores become more complex and an increasing number of these cores are ...