High-speed DSP applied to a multimedia chip set
David B. Chester · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1996
The hardware portion of the Harris Semiconductor Personal Computer Multimedia System is a 5 chip set which implements, in conjunction with a host processor and associated software and firmware, a complete H.320 video teleconferencing capability over ISDN 2B lines. The chip is comprised of a PAL/NTSC Video Encoder, a PAL/NTSC Video Decoder, a Video Codec, a Bus Interface and Audio Processor chip, and an Audio Codec. All 5 chips in the set are implemented in a 0.5 or 0.6 micron CMOS process. Each of the chips implement digital signal processing algorithms of varying levels of complexity and flexibility. These levels range from standard interpolation and decimation filter implementations found on the Audio Codec to dual programmable digital signal processor cores found on the Bus Interface and Audio Processor chip. A top level description of the chip set architecture is presented, along with a functional description of a typical video teleconferencing system based on this chip set. This is followed by a top level description of the various digital signal processing architectures and approaches used in the individual chips in the chip set.