An architectural design of a wavelet coprocessor
Langi, Kinsner · 1994
A flexible but fast and area-efficient VLSI architecture of a coprocessor to perform the discrete wavelet transform (DWT) can be designed using the pyramidal algorithm, pipelined data path unit, direct memory access, and a single 16-bit integer multiplier and adder/subtracter. A design of a 64-point, 4-coefficient Daubechies DWT is described.>