A programmable unified cache architecture for embedded applications
Afzal Malik, Bill Moyer, Dan Cermak · 2000
Advances in technology have allowed portable electronic devices to become smaller and more complex, placing stringent power and performance requirements on the device's components.The M • CORE M3 architecture was developed specifically for these embedded applications.To address the growing need for longer battery life and higher performance, an 8Kbyte, 4-way setassociative, unified (instruction and data) cache with programmable features was added to the M3 core.These features include write mode selection, way management, and buffer enabling/disabling which allow the architecture to be optimized based on the application's requirements.In this paper, we present the features of the unified cache architecture and illustrate the effect on power and performance through benchmark analysis and actual silicon measurements. A Programmable Unified Cache Architecture for Embedded ApplicationsPermission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee.